The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2023
Filed:
Aug. 25, 2020
Applicant:
Arteris, Inc., Campbell, CA (US);
Inventors:
Moez Cherif, Santa Cruz, CA (US);
Benoit de Lescure, Campbell, CA (US);
Assignee:
ARTERIS, INC., Campbell, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); H04L 41/12 (2022.01); G06F 30/392 (2020.01); G06F 30/327 (2020.01); G06F 30/394 (2020.01); G06F 115/02 (2020.01); G06F 115/12 (2020.01); G06F 111/04 (2020.01);
U.S. Cl.
CPC ...
H04L 41/12 (2013.01); G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 2111/04 (2020.01); G06F 2115/02 (2020.01); G06F 2115/12 (2020.01);
Abstract
A system and methods are disclosed that generate a physical roadmap for the connectivity of a network, such as a network-on-chip (NoC). The roadmap includes a set of possible positions for placement of edges and nodes, which are known to be an acceptable and good position for placement of these network elements, that honors the constraints of the network. These known positions are made available to the system for synthesis of the network and generating the connectivity and placement based on the physical roadmap.