The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2023

Filed:

Oct. 23, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Karthik Balakrishnan, Scarsdale, NY (US);

Bahman Hekmatshoartabari, White Plains, NY (US);

Alexander Reznicek, Troy, NY (US);

Jeng-Bang Yau, Yorktown Heights, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 27/108 (2006.01); H01L 29/06 (2006.01); B82Y 10/00 (2011.01); H01L 29/40 (2006.01); H01L 29/739 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66977 (2013.01); B82Y 10/00 (2013.01); H01L 27/10802 (2013.01); H01L 29/0676 (2013.01); H01L 29/083 (2013.01); H01L 29/401 (2013.01); H01L 29/423 (2013.01); H01L 29/42392 (2013.01); H01L 29/66356 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/7391 (2013.01); H01L 29/78642 (2013.01); H01L 29/78645 (2013.01);
Abstract

A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.


Find Patent Forward Citations

Loading…