The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2023
Filed:
Jul. 27, 2021
Applicant:
Stmicroelectronics International N.v., Geneva, CH;
Inventors:
Venkata Narayanan Srinivasan, Greater Noida, IN;
Balwinder Singh Soni, Haryana, IN;
Avneep Kumar Goyal, Greater Noida, IN;
Assignee:
STMicroelectronics International N.V., Geneva, CH;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/38 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 29/14 (2006.01); G11C 29/36 (2006.01); G11C 29/12 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G11C 7/1084 (2013.01); G11C 7/22 (2013.01); G11C 29/14 (2013.01); G11C 29/36 (2013.01); G11C 2029/1206 (2013.01); G11C 2029/3602 (2013.01); H03K 19/20 (2013.01);
Abstract
Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.