The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

Jan. 08, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Ping-Wei Wang, Hsin-Chu, TW;

Chih-Chuan Yang, Hsinchu, TW;

Lien Jung Hung, Taipei, TW;

Feng-Ming Chang, Hsinchu County, TW;

Kuo-Hsiu Hsu, Taoyuan County, TW;

Kian-Long Lim, Hsinchu, TW;

Ruey-Wen Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); G11C 11/41 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); G11C 11/418 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1108 (2013.01); G11C 11/418 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.


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