The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2023

Filed:

Mar. 24, 2021
Applicant:

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Venkata Narayanan Srinivasan, Greater Noida, IN;

Mayankkumar Hareshbhai Niranjani, Lathi, IN;

Gourav Garg, Kaithal, IN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/56 (2006.01); G01R 31/28 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G05F 1/562 (2013.01); G01R 31/2856 (2013.01); G01R 31/2896 (2013.01); H03K 19/20 (2013.01);
Abstract

A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.


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