The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Oct. 21, 2020
Applicant:

Icemos Technology Limited, Belfast, GB;

Inventor:

Samuel J. Anderson, Tempe, AZ (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/76 (2006.01); H01L 29/16 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7606 (2013.01); H01L 21/02378 (2013.01); H01L 21/02381 (2013.01); H01L 21/02389 (2013.01); H01L 21/02392 (2013.01); H01L 21/02395 (2013.01); H01L 21/02527 (2013.01); H01L 29/1602 (2013.01); H01L 29/1606 (2013.01); H01L 29/66045 (2013.01);
Abstract

A semiconductor device has a substrate and graphene with semiconducting properties or diamond region formed on the substrate. The graphene with semiconducting properties or diamond region is formed on or within the substrate using liquid-phase-epitaxy growth of graphene enabled by a catalytic alloy of Ni and Cu. The substrate can be silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, or indium phosphide. A semiconductor component is formed over the graphene with semiconducting properties or diamond region and substrate. The semiconductor component can be a power MOSFET, IGBT, or CTIGBT with a gate structure formed over the substrate, source region adjacent to the gate structure, and drain region adjacent to the gate structure opposite the source region. The graphene with semiconducting properties or diamond region is formed under a gate of the MOSFET to reduce drain to source resistance, as well as providing radiation hardening for the device.


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