The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Jan. 28, 2021
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Wei-Chih Chuang, Tainan, TW;

Chia-Jong Liu, Ping-Tung County, TW;

Kuang-Hsiu Chen, Tainan, TW;

Chung-Ting Huang, Kaohsiung, TW;

Chi-Hsuan Tang, Kaohsiung, TW;

Kai-Hsiang Wang, Taichung, TW;

Bing-Yang Jiang, Tainan, TW;

Yu-Lin Cheng, Changhua County, TW;

Chun-Jen Chen, Tainan, TW;

Yu-Shu Lin, Tainan, TW;

Jhong-Yi Huang, Nantou County, TW;

Chao-Nan Chen, Tainan, TW;

Guan-Ying Wu, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6656 (2013.01); H01L 29/42364 (2013.01);
Abstract

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first spacer and a second spacer around the gate structure; forming a recess adjacent to two sides of the second spacer; performing a cleaning process to trim the second spacer for forming a void between the first spacer and the substrate; and forming an epitaxial layer in the recess.


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