The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Apr. 14, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yoh-Rong Liu, Hsinchu, TW;

Wen-Kai Lin, Yilan County, TW;

Che-Hao Chang, Hsinchu, TW;

Chi On Chui, Hsinchu, TW;

Yung-Cheng Lu, Hsinchu, TW;

Li-Chi Yu, Jhubei, TW;

Sen-Hong Syue, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 21/8234 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66553 (2013.01); H01L 21/823412 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.


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