The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Jun. 29, 2021
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Steven M. Shank, Jericho, VT (US);

Anthony K. Stamper, Williston, VT (US);

Venkata N. R. Vanukuru, Karnataka, IN;

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2012.01); H01L 29/06 (2006.01); H01L 27/118 (2006.01); H01L 21/762 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/762 (2013.01); H01L 27/088 (2013.01); H01L 27/11803 (2013.01); H01L 2027/11831 (2013.01);
Abstract

Structures for a semiconductor device including airgap isolation and methods of forming a semiconductor device structure that includes airgap isolation. The structure includes a trench isolation region, an active region of semiconductor material surrounded by the trench isolation region, and a field-effect transistor including a gate within the active region. The structure further includes a dielectric layer over the field-effect transistor, a first gate contact coupled to the gate, and a second gate contact coupled to the gate. The first and second gate contacts are positioned in the dielectric layer over the active region, and the second gate contact is spaced along a longitudinal axis of the gate from the first gate contact. The structure further includes an airgap including a portion positioned in the dielectric layer over the gate between the first and second gate contacts.


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