The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Sep. 10, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Aniket Patil, San Diego, CA (US);

Hong Bok We, San Diego, CA (US);

Kuiwon Kang, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 25/16 (2006.01); H01L 25/00 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5385 (2013.01); H01L 23/13 (2013.01); H01L 23/3128 (2013.01); H01L 23/49833 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 25/162 (2013.01); H01L 25/165 (2013.01); H01L 25/50 (2013.01); H01L 23/49816 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01);
Abstract

A package that includes a substrate and an integrated device. The substrate includes a core portion, a first substrate portion and a second substrate portion. The core portion includes a core layer and core interconnects. The first substrate portion is coupled to the core portion. The first substrate portion includes at least one first dielectric layer coupled to the core layer, and a first plurality of interconnects located in the at least one first dielectric layer. The second substrate portion is coupled to the core portion. The second substrate includes at least one second dielectric layer coupled to the core layer, and a second plurality of interconnects located in the at least one second dielectric layer. The core portion and the second substrate portion include a cavity. The integrated device is coupled to the first substrate portion through the cavity of the second substrate portion and the core portion.


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