The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Jul. 28, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Wen Yin, Chandler, AZ (US);

Yonghao An, San Diego, CA (US);

Reynante Tamunan Alvarado, Escondido, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 21/56 (2006.01); H01L 23/552 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3677 (2013.01); H01L 21/56 (2013.01); H01L 23/552 (2013.01); H01L 24/32 (2013.01); H01L 24/43 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/43847 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/4912 (2013.01); H01L 2224/49051 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92247 (2013.01);
Abstract

A package that includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.


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