The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2023

Filed:

Mar. 24, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Ferdinando Bedeschi, Biassono, IT;

Efrem Bolandrina, Fiorano al Serio, IT;

Umberto Di Vincenzo, Capriate San Gervasio, IT;

Riccardo Muzzetto, Arcore, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 16/04 (2006.01); G11C 16/32 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0433 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01);
Abstract

A memory device with single transistor drivers and methods to operate the memory device are described. In some embodiments, the memory device may comprise memory cells at cross points of access lines of a memory array, a first even single transistor driver configured to drive a first even access line to a discharging voltage during an IDLE phase, to drive the first even access line to a floating voltage during an ACTIVE phase, and to drive the first even access line to a read/program voltage during a PULSE phase, and a first odd single transistor driver configured to drive a first odd access line, the first odd access line physically adjacent to the first even access line, to the discharging voltage during the IDLE phase, to drive the first odd access line to the floating voltage during the ACTIVE phase, and to drive the first odd access line to a shielding voltage during the PULSE phase.


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