The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

May. 11, 2021
Applicant:

Kepler Computing Inc., San Francisco, CA (US);

Inventors:

Sasikanth Manipatruni, Portland, OR (US);

Rafael Rios, Austin, TX (US);

Ikenna Odinaka, Durham, NC (US);

Robert Menezes, Portland, OR (US);

Rajeev Kumar Dokania, Beaverton, OR (US);

Ramamoorthy Ramesh, Moraga, CA (US);

Amrita Mathuriya, Portland, OR (US);

Assignee:

Kepler Computing Inc., San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/23 (2006.01); H03K 19/00 (2006.01); H01L 49/02 (2006.01); H01L 29/51 (2006.01); H03K 19/20 (2006.01); H01L 27/11502 (2017.01); G11C 11/16 (2006.01); G11C 19/08 (2006.01); H01L 27/22 (2006.01); H03K 19/16 (2006.01); H03K 19/003 (2006.01); H03K 19/01 (2006.01);
U.S. Cl.
CPC ...
H03K 19/23 (2013.01); G11C 11/161 (2013.01); G11C 19/0841 (2013.01); H01L 27/11502 (2013.01); H01L 27/22 (2013.01); H01L 28/55 (2013.01); H01L 28/75 (2013.01); H01L 29/516 (2013.01); H03K 19/003 (2013.01); H03K 19/01 (2013.01); H03K 19/16 (2013.01); H03K 19/20 (2013.01);
Abstract

A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates and threshold gates. Input signals in the form of analog, digital, or combination of them are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a capacitor comprising non-linear polar material. The second terminal of the capacitor provides the output of the logic gate, which can be driven by any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. Any suitable logic or analog circuit can drive the output and inputs of the majority logic gate. As such, the majority gate of various embodiments can be combined with existing transistor technologies.


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