The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Dec. 11, 2020
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Sipeng Gu, Clifton Park, NY (US);

Yi Zheng, Sunnyvale, CA (US);

Qintao Zhang, Mt Kisco, NY (US);

John Hautala, Beverly, MA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66734 (2013.01); H01L 21/265 (2013.01); H01L 29/4236 (2013.01); H01L 29/7813 (2013.01);
Abstract

Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming a gate spacer layer over the device structure, and removing the gate spacer layer from a top surface of the device structure and from a first section of each of the plurality of trenches, wherein a portion of the gate spacer layer remains along a second section of each of the plurality of trenches. The method may further include forming a gate oxide layer along the first section of each of the plurality of trenches and along the portion of the gate spacer layer.


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