The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Jun. 29, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chien-Min Lee, Hsinchu County, TW;

Ming-Yuan Song, Hsinchu, TW;

Yen-Lin Huang, Hsinchu, TW;

Shy-Jay Lin, Hsinchu County, TW;

Tung-Ying Lee, Hsinchu, TW;

Xinyu Bao, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/16 (2006.01); H01L 27/22 (2006.01); H01L 43/04 (2006.01); H01L 43/06 (2006.01); G11C 11/18 (2006.01); H01L 43/14 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/18 (2013.01); H01L 43/04 (2013.01); H01L 43/06 (2013.01); H01L 43/14 (2013.01);
Abstract

Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.


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