The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Aug. 31, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kamal M. Karda, Boise, ID (US);

Deepak Chandra Pandey, ALmora, IN;

Litao Yang, Boise, ID (US);

Srinivas Pulugurtha, Boise, ID (US);

Yunfei Gao, Boise, ID (US);

Haitao Liu, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 49/02 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10805 (2013.01); H01L 21/0228 (2013.01); H01L 21/02186 (2013.01); H01L 21/02189 (2013.01); H01L 21/02192 (2013.01); H01L 21/02603 (2013.01); H01L 27/1085 (2013.01); H01L 27/10873 (2013.01); H01L 28/60 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. In one example, an insulator material is formed on a surface of the first source/drain region and a conductor material formed on the insulator material to form a metal insulator semiconductor (MIS) interface between the horizontally oriented digit lines and the first source/drain regions of the horizontally oriented access devices.


Find Patent Forward Citations

Loading…