The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2022

Filed:

Dec. 14, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gilbert Dewey, Beaverton, OR (US);

Telesphor Kamgaing, Chandler, AZ (US);

Aleksandar Aleksov, Chandler, AZ (US);

Gerogios Dogiamis, Chandler, AZ (US);

Hyung-Jin Lee, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/00 (2006.01); H01L 27/07 (2006.01); H01L 21/8238 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0705 (2013.01); H01L 21/823871 (2013.01); H01L 23/5384 (2013.01); H01L 24/17 (2013.01); H01L 24/81 (2013.01); H01L 25/074 (2013.01); H01L 29/16 (2013.01); H01L 29/20 (2013.01); H01L 29/7851 (2013.01);
Abstract

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment the semiconductor device comprises a first semiconductor layer, where first transistors are fabricated in the first semiconductor layer, and a back end stack over the first transistors. In an embodiment the back end stack comprises conductive traces and vias electrically coupled to the first transistors. In an embodiment, the semiconductor device further comprises a second semiconductor layer over the back end stack, where the second semiconductor layer is a different semiconductor than the first semiconductor layer. In an embodiment, second transistors are fabricated in the second semiconductor layer.


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