The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2022
Filed:
Jul. 06, 2020
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/792 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 27/06 (2006.01); H01L 27/11578 (2017.01); B82Y 10/00 (2011.01); G06F 3/06 (2006.01); G11C 13/02 (2006.01); G11C 14/00 (2006.01); G11C 15/04 (2006.01); H01L 27/11514 (2017.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0669 (2013.01); B82Y 10/00 (2013.01); G06F 3/0679 (2013.01); G06F 3/0688 (2013.01); G11C 13/025 (2013.01); G11C 14/009 (2013.01); G11C 14/0018 (2013.01); G11C 15/046 (2013.01); H01L 21/02491 (2013.01); H01L 27/0688 (2013.01); H01L 27/11514 (2013.01); H01L 27/11578 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/78654 (2013.01); H01L 29/78696 (2013.01); H01L 29/792 (2013.01); H01L 29/0673 (2013.01); H01L 29/66833 (2013.01); H01L 2029/7857 (2013.01);
Abstract
Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.