The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2022
Filed:
Jan. 08, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Aaron Lilak, Beaverton, OR (US);
Patrick Keys, Portland, OR (US);
Sean Ma, Portland, OR (US);
Stephen Cea, Hillsboro, OR (US);
Rishabh Mehandru, Portland, OR (US);
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/306 (2006.01); H01L 21/3105 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0673 (2013.01); H01L 21/30604 (2013.01); H01L 21/31053 (2013.01); H01L 21/568 (2013.01); H01L 21/7806 (2013.01); H01L 23/3107 (2013.01); H01L 27/0886 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract
An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.