The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

May. 29, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Kuo-Hsiu Hsu, Taoyuan County, TW;

Feng-Ming Chang, Hsinchu County, TW;

Kian-Long Lim, Hsinchu, TW;

Ping-Wei Wang, Hsin-Chu, TW;

Lien Jung Hung, Taipei, TW;

Ruey-Wen Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); H01L 27/11 (2006.01); G11C 8/08 (2006.01); G11C 11/412 (2006.01); G11C 11/417 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 11/412 (2013.01); G11C 11/417 (2013.01);
Abstract

A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, first and second pass-gate (PG) transistors, and bit line (BL) conductors. The first PU and the first PD transistors form a first inverter. The second PU and the second PD transistors form a second inverter. The first and the second inverters are cross-coupled to form two storage nodes that are coupled to the BL conductors through the first and the second PG transistors. The first and the second PU transistors are formed over an n-type active region over a frontside of the semiconductor structure. The first and the second PD transistors and the first and the second PG transistors are formed over a p-type active region over the frontside of the semiconductor structure. The BL conductors are disposed over a backside of the semiconductor structure.


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