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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11527432 B1

PDFFull Text
Date of Patent:
Dec. 13, 2022

Filed:

Nov. 02, 2020

Bulk substrates with a self-aligned buried polycrystalline layer

Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Steven M. Shank, Jericho, VT (US);

Anthony K. Stamper, Williston, VT (US);

Ian McCallum-Cook, Burlington, VT (US);

Siva P. Adusumilli, South Burlington, VT (US);

Assignee:

GlobalFoundries U.S. Inc., Santa Clara, CA (US);

Attorneys:

Thompson Hine LLP

Anthony Canale

Primary Examiner:

Walter H Swanson

Int. Cl.
CPC ...
H01L 21/763 (2006.01); H01L 29/06 (2006.01); H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 21/324 (2006.01); H01L 21/84 (2006.01); H01L 21/265 (2006.01); H01L 21/74 (2006.01); H01L 29/32 (2006.01); H01L 21/02 (2006.01); H01L 27/06 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 21/763 (2013.01); H01L 21/26506 (2013.01); H01L 21/26526 (2013.01); H01L 21/26533 (2013.01); H01L 21/324 (2013.01); H01L 21/743 (2013.01); H01L 21/76267 (2013.01); H01L 21/76283 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/0642 (2013.01); H01L 29/0649 (2013.01); H01L 29/32 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 21/02271 (2013.01); H01L 27/0629 (2013.01); H01L 29/1087 (2013.01);
Abstract

Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

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