The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Apr. 15, 2021
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Ke Liang, Wuhan, CN;

Chunyuan Hou, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/00 (2006.01); G11C 16/14 (2006.01); G11C 16/04 (2006.01); H01L 27/11582 (2017.01); G11C 11/56 (2006.01); H01L 27/11556 (2017.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/0483 (2013.01); G11C 11/5635 (2013.01); G11C 11/5671 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01);
Abstract

In certain aspects, a memory device includes an array of memory cells including a plurality of rows of memory cells, a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform an erase operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line. To perform the erase operation, the peripheral circuit is configured to discharge an unselected word line coupled to an unselected row of memory cells of the plurality of rows of memory cells from an initial voltage to a discharge voltage in a first time period, and float the unselected word line in a second time period after the first time period.


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