The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2022

Filed:

Sep. 27, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Zhe Wang, Portland, OR (US);

Alaa R. Alameldeen, Hillsboro, OR (US);

Yi Zou, Portland, OR (US);

Gordon King, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0811 (2016.01); G06F 12/0873 (2016.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01); G06F 12/0897 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0873 (2013.01); G06F 12/0246 (2013.01); G06F 12/0811 (2013.01); G06F 12/0897 (2013.01); G06F 13/1668 (2013.01); G06F 2212/1021 (2013.01);
Abstract

An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.


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