The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2022

Filed:

Oct. 18, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Cheng Ho, Hsinchu, TW;

Ming-Shiang Lin, Hsinchu, TW;

Jin Cai, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/02181 (2013.01); H01L 21/02321 (2013.01); H01L 29/517 (2013.01); H01L 29/66795 (2013.01);
Abstract

A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.


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