The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2022

Filed:

Oct. 30, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Scott William Jessen, Allen, TX (US);

Tae Seung Kim, Austin, TX (US);

Steven Lee Prins, Fairview, TX (US);

Can Duan, Richardson, TX (US);

Abbas Ali, Plano, TX (US);

Erich Wesley Kinder, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 21/8234 (2006.01); H01L 27/12 (2006.01); H01L 27/01 (2006.01); H01L 21/3213 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 28/20 (2013.01); H01L 21/8234 (2013.01); H01L 27/016 (2013.01); H01L 27/1207 (2013.01); H01L 21/31116 (2013.01); H01L 21/32139 (2013.01);
Abstract

A method of fabricating an integrated circuit (IC) includes forming a dielectric layer on a substrate having a plurality of the IC. A thin-film resistor (TFR) layer is deposited on the dielectric layer, and an underlayer (UL) including carbon is formed on the TFR layer. A hard mask layer including silicon is formed on the UL. Masked etching of the hard mask layer transfers a pattern of a photoresist layer onto the hard mask layer to form a hard mask layer pattern. Masked etching of the UL transfers the hard mask layer pattern onto the UL to form a UL pattern. Masked etching of the TFR layer transfers the UL pattern onto the TFR layer to form a TFR layer pattern including a matched pair of TFRs. The matched pair of TFRs are generally included in circuitry configured together for implementing at least one function.


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