The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2022

Filed:

Dec. 23, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

William J. Gallagher, Hsinchu, TW;

Shy-Jay Lin, Jhudong Township, TW;

Ming Yuan Song, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/02 (2006.01); H01L 27/22 (2006.01); H01L 43/14 (2006.01); H01L 43/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); H01L 43/04 (2013.01); H01L 43/14 (2013.01);
Abstract

Various embodiments of the present disclosure are directed towards a memory device including a shunting layer overlying a spin orbit torque (SOT) layer. A magnetic tunnel junction (MTJ) structure overlies a semiconductor substrate. The MTJ structure includes a free layer, a reference layer, and a tunnel barrier layer disposed between the free and reference layers. A bottom electrode via (BEVA) underlies the MTJ structure, where the BEVA is laterally offset from the MTJ structure by a lateral distance. The SOT layer is disposed vertically between the BEVA and the MTJ structure, where the SOT layer continuously extends along the lateral distance. The shunting layer extends across an upper surface of the SOT layer and extends across at least a portion of the lateral distance.


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