The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2022

Filed:

Nov. 29, 2019
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Ahmed M. Shebaita, Fremont, CA (US);

Han Y. Koh, Fremont, CA (US);

Li Ding, San Jose, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 119/12 (2020.01); G06F 30/398 (2020.01); H03K 19/0948 (2006.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/398 (2020.01); H03K 19/0948 (2013.01); G06F 2119/12 (2020.01);
Abstract

Techniques and systems for determining an output waveform at an output of a complementary metal-oxide-semiconductor (CMOS) logic gate are described. Some embodiments can identify at least one set of inputs of the CMOS logic gate that, when switched together, causes multiple transistors coupled in parallel to simultaneously turn-on and drive the output of the CMOS logic gate. Next, the embodiments can determine a set of current source models that are coupled in parallel to model the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together. The embodiments can then simulate the set of current source models together to determine the output waveform at the output of the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together.


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