The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2022

Filed:

Mar. 09, 2021
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

David Clarke, Dublin, IE;

Peter McColgan, Dublin, IE;

Zachary Dickman, Dublin, IE;

Jose Marques, Dublin, IE;

Juan J. Noguera Serra, San Jose, CA (US);

Tim Tuan, San Jose, CA (US);

Baris Ozgul, Dublin, IE;

Jan Langer, Chemnitz, DE;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 13/28 (2013.01);
Abstract

An integrated circuit having a data processing engine (DPE) array can include a plurality of memory tiles. A first memory tile can include a first direct memory access (DMA) engine, a first random-access memory (RAM) connected to the first DMA engine, and a first stream switch coupled to the first DMA engine. The first DMA engine may be coupled to a second RAM disposed in a second memory tile. The first stream switch may be coupled to a second stream switch disposed in the second memory tile.


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