The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

Jun. 29, 2021
Applicants:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

International Business Machines Corporation, Yorktown, NY (US);

Inventors:

Shay Reboh, La Buisse, FR;

Remi Coquand, Le Touvet, FR;

Nicolas Loubet, Albany, NY (US);

Tenko Yamashita, Albany, NY (US);

Jingyun Zhang, Albany, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/76 (2006.01); H01L 29/775 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0673 (2013.01); H01L 21/823431 (2013.01); H01L 27/0688 (2013.01); H01L 27/0886 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/7613 (2013.01); H01L 29/775 (2013.01);
Abstract

An electronic device including at least first and second superimposed transistors comprises at least a substrate; a first transistor including a portion of a first nanowire forming a first channel, and first source and drain regions in contact with ends of the first nanowire portion; and a second transistor including a portion of a second nanowire forming a second channel and having a greater length than that of the first channel, and second source and drain regions in contact with ends of the second nanowire portion such that the second transistor is arranged between the substrate and the first transistor. A dielectric encapsulation layer covers at least the second source and drain regions and such that the first source and drain regions are arranged at least partly on the dielectric encapsulation layer, and forms vertical insulating portions extending between the first and second source and drain regions.


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