The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

May. 24, 2019
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Francisco Javier Santos Rodriguez, Villach, AT;

Alexander Breymesser, Villach, AT;

Erich Griebl, Dorfen, DE;

Michael Knabl, Finkenstein, AT;

Matthias Kuenle, Villach, AT;

Andreas Moser, Maria-Rain, AT;

Roland Rupp, Lauf, DE;

Hans-Joachim Schulze, Taufkirchen, DE;

Sokratis Sgouridis, Annenheim, AT;

Stephan Voss, Munich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/16 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/16 (2013.01);
Abstract

A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.


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