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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11515258 B1

PDFFull Text
Date of Patent:
Nov. 29, 2022

Filed:

Sep. 21, 2020

Package substrate and manufacturing method thereof

Applicant:

Zhuhai Access Semiconductor Co., Ltd, Zhuhai, CN;

Inventors:

Xianming Chen, Zhuhai, CN;

Yejie Hong, Zhuhai, CN;

Benxia Huang, Zhuhai, CN;

Lei Feng, Zhuhai, CN;

Assignee:

ZHUHAI ACCESS SEMICONDUCTOR CO., LTD, Zhuhai, CN;

Attorney:

The Dobrusin Law Firm, P.C.

Primary Examiner:

Quoc D Hoang

Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/50 (2006.01); H01L 21/768 (2006.01); H01L 23/15 (2006.01); H01L 23/00 (2006.01); H01L 21/60 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 21/50 (2013.01); H01L 21/76802 (2013.01); H01L 23/15 (2013.01); H01L 24/14 (2013.01); H01L 21/60 (2021.08);
Abstract

A method for manufacturing a package substrate, includes: providing a glass frame having a through hole and a chip embedding cavity; fixing an electronic component in the chip embedding cavity; coating a dielectric layer to an upper surface of the glass frame, the through hole and the chip embedding cavity and curing the dielectric layer; photoetching the dielectric layer to form an opening window arranged above the through hole; depositing metal through the opening window and patterning the metal to form a metal pillar and a circuit layer, the metal pillar passing through the through hole, the circuit layer being arranged on the upper surface and/or a lower surface of the glass frame and being connected to the electronic component and the metal pillar; forming a solder mask on a surface of the circuit layer, patterning the solder mask to form a pad connected to the circuit layer.

Find Patent Forward Citations

Chen, Xianming. (2022). Package substrate and manufacturing method thereof (U.S. Patent No. 11515258). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11515258

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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