The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

Feb. 17, 2021
Applicant:

Sumitomo Electric Device Innovations, Inc., Kanagawa, JP;

Inventors:

Toshiyuki Kosaka, Yokohama, JP;

Shunsuke Kurachi, Yokohama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 21/285 (2006.01); H01L 21/288 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 21/288 (2013.01); H01L 21/2855 (2013.01); H01L 24/80 (2013.01);
Abstract

A semiconductor device that comprises a substrate with a primary surface and a secondary surface opposite to the primary surface. The primary surface provides a semiconductor active device. The semiconductor device includes a base metal layer deposited on the secondary surface and within the substrate via in which a vacancy is formed, and an additional metal layer on the base metal layer, the additional metal layer having different wettability against a solder as compared to the base metal layer whereby the solder is contactable by the base metal layer and repelled by the additional metal layer. The semiconductor device is die-bonded on the assembly substrate by interposing the solder between the secondary surface and the assembly substrate. The base metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the additional metal layer is in contact with the solder.


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