The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

Apr. 29, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yoshiaki Fukuzumi, Kanagawa, JP;

Paolo Tessariol, Arcore, IT;

David H. Wells, Boise, ID (US);

Lars P. Heineck, Boise, ID (US);

Richard J. Hill, Boise, ID (US);

Lifang Xu, Boise, ID (US);

Indra V. Chary, Boise, ID (US);

Emilio Camerlenghi, Bergamo, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 5/06 (2006.01); H01L 21/50 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G11C 5/06 (2013.01); H01L 21/50 (2013.01); H01L 25/0657 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01);
Abstract

Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.


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