The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2022
Filed:
Feb. 26, 2021
Intel Corporation, Santa Clara, CA (US);
Rajesh M. Sankaran, Portland, OR (US);
David J. Harriman, Portland, OR (US);
Sean O. Stalley, Hillsboro, OR (US);
Rupin H. Vakharwala, Hillsboro, OR (US);
Ishwar Agarwal, Portland, OR (US);
Pratik M. Marolia, Hillsboro, OR (US);
Stephen R. Van Doren, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.