The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2022
Filed:
Sep. 21, 2020
Intel Corporation, Santa Clara, CA (US);
Ren Wang, Portland, OR (US);
Andrew J. Herdrich, Hillsboro, OR (US);
Yen-cheng Liu, Portland, OR (US);
Herbert H. Hum, Portland, OR (US);
Jong Soo Park, Santa Clara, CA (US);
Christopher J. Hughes, Santa Clara, CA (US);
Namakkal N. Venkatesan, Hillsboro, OR (US);
Adrian C. Moga, Portland, OR (US);
Aamer Jaleel, Northborough, MA (US);
Zeshan A. Chishti, Hillsboro, OR (US);
Mesut A. Ergin, Portland, OR (US);
Jr-shian Tsai, Portland, OR (US);
Alexander W. Min, Portland, OR (US);
Tsung-yuan C. Tai, Portland, OR (US);
Christian Maciocco, Portland, OR (US);
Rajesh Sankaran, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.