The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2022

Filed:

Sep. 30, 2020
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Rong Chen, San Jose, CA (US);

He Xiao, Sunnyvale, CA (US);

Nenad Nedeljkovic, Mountain View, CA (US);

Nupur B. Andrews, Los Altos, CA (US);

Dan Nicolaescu, Fair Oaks, CA (US);

James Sangkyu Kim, San Jose, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/445 (2018.01); G06F 8/41 (2018.01);
U.S. Cl.
CPC ...
G06F 9/44521 (2013.01); G06F 8/41 (2013.01);
Abstract

An approach includes the use of a description of instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions. In some embodiments, the instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions are described using a single language. These descriptions are then compiled into other languages for use in tool chains for generating simulators (a hardware and instruction set simulator and a hardware accelerator simulator). In some embodiments, the approach illustrated herein can be combined with state machine functionality to manage the execution of instructions that require multiple states. In some embodiments, the approach illustrated herein can be combined with an external register file for transferring information between a processor and a hardware accelerator.


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