The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2022
Filed:
Oct. 12, 2020
Applicant:
Semiconductor Components Industries, Llc, Phoenix, AZ (US);
Inventors:
Yusheng Lin, Phoenix, AZ (US);
Soon Wei Wang, Seremban, MY;
Chee Hiong Chew, Seremban, MY;
Francis J. Carney, Mesa, AZ (US);
Assignee:
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Phoenix, AZ (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/544 (2006.01);
U.S. Cl.
CPC ...
H01L 24/02 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/6836 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/3185 (2013.01); H01L 23/544 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/94 (2013.01); H01L 24/96 (2013.01); H01L 2221/68327 (2013.01); H01L 2223/5448 (2013.01); H01L 2223/54406 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/024 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02315 (2013.01); H01L 2224/0346 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05571 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/05655 (2013.01); H01L 2224/11334 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/94 (2013.01); H01L 2224/96 (2013.01);
Abstract
A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.