The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

May. 14, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jungeun Koo, Hwaseong-si, KR;

Yechung Chung, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01); H01L 23/49 (2006.01); H01L 25/07 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 22/32 (2013.01); H01L 23/49 (2013.01); H01L 23/4985 (2013.01); H01L 24/32 (2013.01); H01L 25/072 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 2224/32227 (2013.01); H01L 2924/1426 (2013.01);
Abstract

A chip-on-film package includes a base film having a top surface and a bottom surface, and a circuit region; a source driver chip and a gate driver chip mounted on the circuit region; a first conductive line on the top surface of the base film, a second conductive line on the bottom surface of the base film, and a conductive via that connects the first and second conductive lines to each other; a first row of bonding pads on the circuit region and connected to the source driver chip; a second row of bonding pads on the circuit region and connected to the source driver chip and the gate driver chip; and a test pad outside the circuit region and connected to the first and second conductive lines and the conductive via.


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