The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2022

Filed:

Aug. 18, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Jason M. Johnson, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/38 (2006.01); G01R 31/317 (2006.01); G06F 11/10 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G01R 31/31712 (2013.01); G06F 11/1068 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01);
Abstract

Memory devices are disclosed. A memory device may include a number of column planes, and at least one circuit. The at least one circuit may be configured to receive test result data for a column address for each column plane of the number of column planes of the memory array. The at least one circuit may also be configured to convert the test result data to a first result responsive to only one bit of a number of bits of the number of column planes failing a test for the column address. Further, the at least one circuit may be configured to convert the test result data to a second result responsive to only one column plane failing the test for the column address and more than one bit of the one column plane being defective. Methods of testing a memory device, and electronic systems are also disclosed.


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