The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2022
Filed:
Nov. 13, 2020
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Harry-Hak-Lay Chuang, Hsinchu County, TW;
Sheng-Wen Fu, Hsinchu, TW;
Jun-Yao Chen, Taoyuan, TW;
Sheng-Huang Huang, Hsinchu, TW;
Hung-Cho Wang, Taipei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
A method for fabricating an integrated circuit is provided. The method includes depositing an etch stop layer over an interconnect layer having a conductive feature; depositing a protective layer over the etch stop layer; depositing a first dielectric layer over the protective layer; etching a via opening in the first dielectric layer, wherein the protective layer has a higher etch resistance to etching the via opening than that of the first dielectric layer; etching a portion of the protective layer exposed by the via opening; etching a portion of the etch stop layer exposed by the via opening, such that the via opening exposes the conductive feature; forming a bottom electrode via in the via opening; and forming a memory stack over the bottom electrode via.