The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Dec. 30, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aleksandar Aleksov, Chandler, AZ (US);

Veronica Strong, Chandler, AZ (US);

Brandon Rawlings, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/14 (2006.01); H01L 23/48 (2006.01); H01L 21/00 (2006.01); H01L 21/4763 (2006.01); H05K 1/00 (2006.01); H01R 9/00 (2006.01); H01L 23/538 (2006.01); H01L 23/498 (2006.01); H01L 27/12 (2006.01); H01L 21/48 (2006.01); H01L 21/027 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5383 (2013.01); H01L 21/0273 (2013.01); H01L 21/4846 (2013.01); H01L 21/4857 (2013.01); H01L 23/481 (2013.01); H01L 23/498 (2013.01); H01L 27/1288 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01);
Abstract

A device package and a method of forming a device package are described. The device package includes a dielectric on a conductive pad, and a first via on a first seed on a top surface of the conductive pad. The device package further includes a conductive trace on the dielectric, and a second via on a second seed layer on the dielectric. The conductive trace connects to the first via and the second via, where the second via connects to an edge of the conductive trace opposite from the first via. The dielectric may include a photoimageable dielectric or a buildup film. The device package may also include a seed on the dielectric prior to the conductive trace on the dielectric, and a second dielectric on the dielectric, the conductive trace, and the first and second vias, where the second dielectric exposes a top surface of the second via.


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