The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2022

Filed:

Jun. 30, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nicholas S. Haehn, Scottsdale, AZ (US);

Edvin Cetegen, Chandler, AZ (US);

Shankar Devasenathipathy, Tempe, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/48 (2006.01); H01L 23/10 (2006.01); H01L 23/538 (2006.01); H01L 23/58 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/10 (2013.01); H01L 21/4846 (2013.01); H01L 23/538 (2013.01); H01L 23/585 (2013.01); H01L 24/13 (2013.01); H01L 25/0655 (2013.01); H01L 2224/13147 (2013.01);
Abstract

An integrated circuit assembly including a substrate having a surface including at least one area including contact points operable for connection with an integrated circuit die; and at least one ring surrounding the at least one area, the at least one ring including an electrically conductive material. A method of forming an integrated circuit assembly including forming a plurality of electrically conductive rings around a periphery of a die area of a substrate selected for attachment of at least one integrated circuit die, wherein the plurality of rings are formed one inside the other; and forming a plurality of contact points in the die area.


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