The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2022
Filed:
Feb. 24, 2020
Intel Corporation, Santa Clara, CA (US);
Christopher J. Hughes, Santa Clara, CA (US);
Joseph Nuzman, Haifa, IL;
Jonas Svennebring, Sollentuna, SE;
Doddaballapur N. Jayasimha, Saratoga, CA (US);
Samantika S. Sury, Westford, MA (US);
David A. Koufaty, Portland, OR (US);
Niall D. McDonnell, Limerick, IE;
Yen-Cheng Liu, Portland, OR (US);
Stephen R. Van Doren, Portland, OR (US);
Stephen J. Robinson, Austin, TX (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.