The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2022

Filed:

Feb. 19, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aaron Lilak, Beaverton, OR (US);

Patrick Keys, Portland, OR (US);

Sayed Hasan, Portland, OR (US);

Stephen Cea, Hillsboro, OR (US);

Anupama Bowonder, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/737 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/02381 (2013.01); H01L 29/086 (2013.01); H01L 29/1045 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/66795 (2013.01); H01L 29/66803 (2013.01); H01L 29/7378 (2013.01); H01L 29/7845 (2013.01);
Abstract

Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.


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