The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2022

Filed:

Apr. 29, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chih-Chien Pan, Taipei, TW;

Li-Hui Cheng, New Taipei, TW;

Chin-Fu Kao, Taipei, TW;

Szu-Wei Lu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 25/065 (2006.01); H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 21/304 (2013.01); H01L 21/30604 (2013.01); H01L 21/561 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/49827 (2013.01); H01L 24/09 (2013.01); H01L 24/81 (2013.01); H01L 24/97 (2013.01); H01L 25/0652 (2013.01);
Abstract

In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.


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