The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2022

Filed:

May. 14, 2019
Applicant:

Shin-etsu Handotai Co., Ltd., Tokyo, JP;

Inventors:

Toshikazu Imai, Chikuma, JP;

Kazuhiko Yoshida, Chikuma, JP;

Miho Niitani, Nagano, JP;

Taishi Wakabayashi, Nagano, JP;

Osamu Ishikawa, Annaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76254 (2013.01); H01L 21/26506 (2013.01);
Abstract

A method for manufacturing a bonded SOI wafer, the method using a silicon single crystal wafer having a resistivity of 100 Ω·cm or more as the base wafer, and including steps of: forming an underlying insulator film on a bonding surface side of the base wafer; depositing a polycrystalline silicon layer on a surface of the underlying insulator film; polishing a surface of the polycrystalline silicon layer; modifying the polycrystalline silicon layer by performing ion implantation on the polished polycrystalline silicon layer to form a modified silicon layer; forming the insulator film on a bonding surface of the bond wafer; bonding the bond wafer and a surface of the modified silicon layer of the base wafer with the insulator film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a bonded SOI wafer excellent in harmonic wave characteristics.


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