The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2022

Filed:

Jun. 22, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Scott Weber, Piedmont, CA (US);

Aravind Dasu, Milpitas, CA (US);

Ravi Gutala, San Jose, CA (US);

Mahesh Iyer, Fremont, CA (US);

Eriko Nurvitadhi, Beaverton, OR (US);

Archanna Srinivasan, San Jose, CA (US);

Sean Atsatt, Santa Cruz, CA (US);

James Ball, Scotts Valley, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17736 (2020.01); H01L 25/18 (2006.01); H03K 19/17768 (2020.01); H03K 19/1776 (2020.01);
U.S. Cl.
CPC ...
H03K 19/1774 (2013.01); H01L 25/18 (2013.01); H03K 19/1776 (2013.01); H03K 19/17768 (2013.01);
Abstract

A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.


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