The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2022
Filed:
May. 09, 2018
Applicant:
Micron Technology, Inc., Boise, ID (US);
Inventors:
William C. Waldrop, Allen, TX (US);
Vijayakrishna J. Vankayala, Allen, TX (US);
Scott E. Smith, Plano, TX (US);
Assignee:
Micron Technology, Inc., Boise, ID (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 29/42 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1032 (2013.01); G11C 29/42 (2013.01);
Abstract
Systems and methods are described, in which a parity error alert timing interlock is provided by first waiting for a timer to count a configured parity error pulse width value and then waiting for any in-progress memory operations to complete before deasserting a parity error alert signal that was asserted in response to the detection of a parity error in a command or address.
Quick Actions:
Waldrop, William. (2022). Methods for parity error alert timing interlock and memory devices and systems employing the same (U.S. Patent No. 11487610). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11487610
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile