The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2022

Filed:

Dec. 23, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ravi Pillarisetty, Portland, OR (US);

Willy Rachmady, Beaverton, OR (US);

Kanwaljit Singh, Rotterdam, NL;

Nicole K. Thomas, Portland, OR (US);

Hubert C. George, Portland, OR (US);

Zachary R. Yoscovits, Beaverton, OR (US);

Roman Caudillo, Portland, OR (US);

Payam Amin, Portland, OR (US);

Jeanette M. Roberts, North Plains, OR (US);

James S. Clarke, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); G06N 10/00 (2022.01); H01L 27/088 (2006.01); H01L 29/12 (2006.01); H01L 29/165 (2006.01); H01L 29/423 (2006.01); H01L 29/43 (2006.01); H01L 29/82 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66977 (2013.01); G06N 10/00 (2019.01); H01L 27/088 (2013.01); H01L 29/127 (2013.01); H01L 29/165 (2013.01); H01L 29/42376 (2013.01); H01L 29/437 (2013.01); H01L 29/82 (2013.01);
Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.


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