The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2022

Filed:

Jul. 17, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Shih-Hao Lin, Hsinchu, TW;

Jui-Lin Chen, Taipei, TW;

Hsin-Wen Su, Hsinchu, TW;

Kian-Long Lim, Hsinchu, TW;

Bwo-Ning Chen, Keelung, TW;

Chih-Hsuan Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/3115 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/0259 (2013.01); H01L 21/02532 (2013.01); H01L 21/31155 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66553 (2013.01); H01L 29/66636 (2013.01); H01L 29/66742 (2013.01); H01L 29/7843 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01);
Abstract

Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.


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